Manufacturing of high performance mixed-mode and radio frequency (RF) CMOS and BiCMOS circuits require high performance passive capacitors with high reliability, high capacitance, and low cost (high manufacturing yield). These three factors can be traded off and are dependent on capacitor geometries. New CMOS technologies offer many options for incorporation of BEOL as well as FEOL passive devices into standard CMOS and BiCMOS to improve circuit integration and performance. For example, high-performance capacitors such as the vertical-parallel plate (VPP) capacitor are suitable for mixed-mode and RF applications.
VPP capacitors use combinations of single level metal capacitor with comb-comb or interdigitated comb-serpentine configurations to boost the capacitance value and density. Vias are used to link multiple metal levels together, and these linked vertical parallel capacitor structures significantly increase the capacitance value but still maintain relative small capacitor's surface area. The overall capacitance of the VPP can be increased by layout optimization.
Manufacturability and cost of quality on chip passive devices are essential to the development of high performance SiGe RF technologies. The VPP capacitor is very promising compared to other capacitor choices due to its relatively low manufacturing cost and simple integration. For the maximum chip performance, the large VPP capacitor (>10E6 μm2 surface area) with large capacitance is required. However, such large capacitor may be exposed to the risks of low yield and high reliability concern. (This is shown in FIG. 5.)